Indiana Integrated Circuits, LLC

www.indianaic.com

Indiana Integrated Circuits, LLC (IIC) was created by two University of Notre Dame researchers for the purpose of commercializing a revolutionary microchip interconnect and packaging technology, Quilt Packaging (QP). Working closely with customers and partners, the IIC team assists in the implementation of QP into existing process flows, performs proof-of-concept prototyping, and develops application-specific solutions for licensees. IIC's patented technology delivers unprecedented microchip integration options to designers, enabled by the ultra-low-loss characteristics of Quilt Packaging interconnections, sub-micron chip-to-chip alignment, and chip-to-chip gaps as small as five microns. In addition to enabling an entirely new class of system designs, utilizing QP can result in significant cost reduction by partitioning large, poorer-yielding chips and “reconstituting” them from smaller, higher yielding chips, without reducing performance or functionality. Improvements in time-to-market, power consumption, form-factor and yield are possible with adoption of QP, as well as an increased flexibility in mixing and matching IP cores and existing designs.

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Indiana Integrated Circuits, LLC (IIC) was created by two University of Notre Dame researchers for the purpose of commercializing a revolutionary microchip interconnect and packaging technology, Quilt Packaging (QP). Working closely with customers and partners, the IIC team assists in the implementation of QP into existing process flows, performs proof-of-concept prototyping, and develops application-specific solutions for licensees. IIC's patented technology delivers unprecedented microchip integration options to designers, enabled by the ultra-low-loss characteristics of Quilt Packaging interconnections, sub-micron chip-to-chip alignment, and chip-to-chip gaps as small as five microns. In addition to enabling an entirely new class of system designs, utilizing QP can result in significant cost reduction by partitioning large, poorer-yielding chips and “reconstituting” them from smaller, higher yielding chips, without reducing performance or functionality. Improvements in time-to-market, power consumption, form-factor and yield are possible with adoption of QP, as well as an increased flexibility in mixing and matching IP cores and existing designs.

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Country

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State

Indiana

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City (Headquarters)

South Bend

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Employees

1-10

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Founded

2009

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  • Principal Research Scientist

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  • Administrative Assistant to Chief Executive Officer

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