PerfectVIPs

www.perfectvips.com

PerfectVIPs is empowering the chip design industry by providing highest quality Verification IP products for Storage applications, Peripheral interconnects and On-Chip bus interfaces. PerfectVIPs products accelerate the chip design & verification cycle with higher reliability and lower risk and cost. To provide robust verification for many interface protocol based designs that reduces design time,design risk and cost of verification, PerfectVIPs has several Verification- IPs called Genie VIPs. PerfectVIPs provides world's largest portfolio of verification IP solutions like PCI-express 3.0,PCI-express 2.0/1.1, USB 3.0, USB 2.0, Ethernet, SPI, AMBA (AHB, APB, & AXI), SMBus, OCP, SAS, SATA, ONFI and Fibre Channel. Each Genie VIP consists of: Bus Functional Model, Protocol Monitor,Checker, comprehensive compliance Test Suite,API,control knobs,error injectors and call back features. All are fully developed in native System Verilog , family of VIPs having flexibility to work with popular languages like VHDL,Verilog,Vera,system C,C++ and ‘e’ and on all commonly used simulators and platforms. "Design Fast Verify Faster"

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PerfectVIPs is empowering the chip design industry by providing highest quality Verification IP products for Storage applications, Peripheral interconnects and On-Chip bus interfaces. PerfectVIPs products accelerate the chip design & verification cycle with higher reliability and lower risk and cost. To provide robust verification for many interface protocol based designs that reduces design time,design risk and cost of verification, PerfectVIPs has several Verification- IPs called Genie VIPs. PerfectVIPs provides world's largest portfolio of verification IP solutions like PCI-express 3.0,PCI-express 2.0/1.1, USB 3.0, USB 2.0, Ethernet, SPI, AMBA (AHB, APB, & AXI), SMBus, OCP, SAS, SATA, ONFI and Fibre Channel. Each Genie VIP consists of: Bus Functional Model, Protocol Monitor,Checker, comprehensive compliance Test Suite,API,control knobs,error injectors and call back features. All are fully developed in native System Verilog , family of VIPs having flexibility to work with popular languages like VHDL,Verilog,Vera,system C,C++ and ‘e’ and on all commonly used simulators and platforms. "Design Fast Verify Faster"

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Country

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State

California

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City (Headquarters)

San Jose

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Founded

2010

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Estimated Revenue

$5,000,000 to $10,000,000

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Social

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Potential Decision Makers

  • Lead Verification Enginee

    Email ****** @****.com
    Phone (***) ****-****
  • Asic Verification Engineer

    Email ****** @****.com
    Phone (***) ****-****
  • Application Specific Integrated Circuit Verification Engineer

    Email ****** @****.com
    Phone (***) ****-****
  • Human Resources Recruiter

    Email ****** @****.com
    Phone (***) ****-****

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