Verific Design Automation, Inc
www.verific.comVerific Design Automation provides (System)Verilog, VHDL, and UPF front-ends to leading EDA, FPGA, and semiconductor companies. Over 80 EDA applications worldwide are using Verific's parsers, analyzers, and elaborators. Its critically acclaimed software is written in C++ and licensed in source code format. APIs are available in C++, Python, and Perl.
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Verific Design Automation provides (System)Verilog, VHDL, and UPF front-ends to leading EDA, FPGA, and semiconductor companies. Over 80 EDA applications worldwide are using Verific's parsers, analyzers, and elaborators. Its critically acclaimed software is written in C++ and licensed in source code format. APIs are available in C++, Python, and Perl.
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Country
State
California
City (Headquarters)
Alameda
Employees
11-50
Founded
1999
Estimated Revenue
$1 to $1,000,000
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Owner
Email ****** @****.comPhone (***) ****-****Chief Operations Officer
Email ****** @****.comPhone (***) ****-****Director
Email ****** @****.comPhone (***) ****-****Director India Operation
Email ****** @****.comPhone (***) ****-****
Technologies
(19)
