Welcome to SiValley Technologies Pvt. Ltd. we are a leading provider of end-to-end services to Semiconductor, EDA companies in Physical Design, Layout Design, Design Verification and CAD Methodology. SiValley provides total solutions for a given requirement, which includes Physical Design, Layout Design, Design Verification and customized turnkey solutions. SiValley’s strategic partnerships with leading technology companies help provide customers with a comprehensive package of end-to-end solutions. At SiValley, we innovate to fulfil the global ASIC design needs with reliable and sustainable solutions. With the highly committed and innovative technical team and technical leadership, SiValley is all set to serve for needs in ASIC Design. Service Offerings ASIC Physical Design:  Floorplanning & Partitioning  Place & Route, CTS  Physical Verification  STA, GDS Generation Layout Design:  Analog, Memory, RF Layout Design  IO Layout, Standard Cell Design  Chip Integration, Chip Sign off and Tapeout  AMS Verification ASIC Design and Verification:  IP Verification  SoC/Subsystem Integration and Verification  DFT  Synthesis, LEC Current Openings: 1. Analog Layout Design Experience: 4 - 12 Years Tools: Cadence Virtuoso 2. Physical Design Experience: 4 - 15 Years Tools: ICC, SoC Encounter, Olympus, Prime Time 3. RTL Verification Experience: 3-5 years Tools: NCSim, QuestaSim, VCS 4. Standardcell Characterization Experience: 3-5 years Tools: Liberate 5. AMS Verification Experience: 3-5 years Tools: Spectre, ADE L, virtuoso, Spice 6. Memory Layout Experience: 2 - 5 years Tools: Cadence Virtuoso 7. DFT Experience: 2 - 5 years Tools: Modus, TetraMax, Tessent Contact: hr@sivalleytech.com or visit http://www.sivalleytech.com/job-opportunities/