Blue Pearl’s Visual Verification Suite is a totally integrated system of RTL structural and formal verification, CDC analysis, timing constraint generation, and debug. Integrated with FPGA vendor and ASIC tool flows, Blue Pearl gives designers the ability to verify as they code, and find and fix design errors at the RTL level faster than any other set of EDA tools. The Blue Pearl Software Suite, which can be customized for ASIC and FPGA checks and libraries, help designers - Find structural and functional RTL errors such as races and incorrect domain crossings. - Extract and analyze finite state machines (FSM) - Perform chip-level clock domain crossing (CDC) checks with the User Grey Cell™ methodology - Reduce design iteration with the automatically generated timing constraints in SDC format