VHDL training for design and verification of FPGAs and ASICs. Check out our on-line and public venue training sessions at http://www.synthworks.com/public_vhdl_courses.htm Core courses: Comprehensive VHDL Introduction - 4 days - Beginners Class Learn VHDL syntax plus the basics of RTL and testbench coding. Students get VHDL hardware experience with our FPGA based lab board. http://www.synthworks.com/comprehensive_vhdl_introduction.htm VHDL Testbenches and Verification - 5 days Learn the latest VHDL verification techniques including transaction-based testing, intelligent testbenches, bus functional modeling, self-checking, data structures (linked-lists, scoreboards, memories), directed, algorithmic, constrained random, and coverage driven random testing, and functional coverage. http://www.synthworks.com/vhdl_testbench_verification.htm VHDL Coding for Synthesis - 4 days Learn VHDL RTL (FPGA and ASIC) coding styles, methodologies, design techniques, problem solving techniques, and advanced language constructs to produce better, faster, and smaller logic. http://www.synthworks.com/vhdl_rtl_synthesis.htm